Imagesource: https://www.intel.com/

A few months back, in Issue #44, we introduced the current pet project of Bruno Levy - @BrunoLevy01 on Twitter.

While his RISC-V implementation has about as much in common with 8 bit systems as an ant has with space travel, the topic is nevertheless not that far away for many of our readers. After all, 8 bit CPUs in particular can still be fully understood by a single person in their lifetime - due to their simple construction. For the modern counterparts from Intel, AMD and Co, this is not true anymore for a long, long time. Especially since most IP cores of current SoCs are external developments, and their complexity is hidden behind a cheque with a whole lot of zeros.

Well, for RISC-V systems the whole thing is true again. The simplest, but also the more complex RISC-V implementations are so (more or less) trivial, that they are relatively quickly overlooked and just as quickly implemented in an emulator or an FPGA. And thanks to a RISC-V capable C compiler, you can also enjoy high-level languages on your homebrew without breaking your own brain’s … brain, trying to figure out assembly instructions using pencil, paper. 🧠

And for exactly this reason, we currently have to refer to Bruno and his DIY RISC-V CPU again. Bruno has been busy, very busy. And since the initial release of his architecture for e.g. the IceStick, he has added a second part, in which you extend the simple architecture into a pipelined processor, with register forwarding and branch prediction.

If this is not enough, you can build your own (to be precise Bruno's own) FPU in part III. Yeah, floating point arithmetic 🧮.

One of the best resources to get started with RISC-V and/or FPGAs. And completely free of charge.

Thank you Mr. Levy!