Imagesource: Derrick Coetzee, CC0, via Wikimedia Commons

Quite unphilosophically, RISV-V has about as much to do with retrocomputing, as an ant has to do with an anteater. But since we are true animal lovers, and anteaters are typically underrepresented in the media, let's break a lance here. For anteaters and RISC-V. 

But seriously: as a modern ISA, RISV-V really has hardly anything to do with 8-bit CPUs. But if you take a closer look, RISV-V is the next logical step if you have left your own CPUs in software or hardware behind, and are looking for something fresh.

The open architecture, the comparatively low complexity and the implementability on FPGAs make RISC-V an interesting platform.

There are many entrants. A particularly worthwhile one comes from Stefan Metzlaf and his colleagues in the form of a simulator.

Their RISC-V Simulator - written in Java - is available as open source on GitHub. And with its simple examples it is perfect for your first experiments.

Any plans for the weekend? No? Well, now have at least one.