Playing with retro machines is one thing. Building such a machine yourself is quite another. But surprisingly, it's easier than you might think.

You may be one of those who have built a working computer using applications like LogiSim, Digital or others. If so, you've probably also thought about getting your creation to work on an FPGA using Verilog or VHDL. 

And that's where a new project for Verilator with SDL comes into play. Verilator generates C++ models from Verilog designs. SDL as a library gives low level access to graphics hardware. The combination of both - brought together by Will Green - opens up whole new possibilities.

Especially the chance to bundle your own LogiSim creation into an independent software - including graphical output.

Your heart beats for FPGAs? Then you can't avoid reading this one.