Imagesource: https://zerotoasiccourse.com/

FPGAs are one thing. A little bit of Verilog, a little bit of time, build, load, fail, repeat. The classic cycle. For ASIC design, that's not quite so true, since once an ASIC is made, it's not easy to fix via an update like an FPGA.

Matthew Venn says of himself, that he is on a mission to make ASICs more accessible. And that's great, because there's not nearly as much material on ASIC design as there is on FPGAs.

Matthew offers a commercial course Zero to ASIC, and if you are curious about the topic, you can find some interesting teaser material on his YouTube Channel.

We’re not sponsored, just thought, this could be interesting.